Oscillators are a key component in the design of radio frequency (RF) communication systems. Accurate knowledge of the modulation gain of an RF oscillator significantly reduces the complexity and increases the performance of the polar transmitter in which the frequency synthesizer is itself a part of the frequency/phase modulation path. It is particularly beneficial in systems implemented in deep submicron CMOS and based on orthogonal frequency/phase and amplitude (i.e. polar) topology. Estimation of RF oscillator frequency-modulation gain is especially important in low-cost high-volume transceivers. In such systems, the phase locked loop sets the loop bandwidth while the transmitter sets the transfer function of the direct frequency modulation path wherein the acceptable gain estimation error ranges from less than 1% for CDMA to several percents for GSM and Bluetooth, for example.
The value of the frequency gain (KDCO) of an RF oscillator, such as a digitally controlled oscillator (DCO), at any point in time is a function of frequency as well as the current state of process, voltage and temperature (PVT). For a two point direct modulation scheme such as used in DRP based radios, the modulation accuracy depends on accurate estimation and calibration of the DCO gain.
The DCO gain normalization functions to decouple the phase and frequency information throughout the system from the process, voltage and temperature variations that normally affect the KDCO. The phase information is normalized to the clock period of the oscillator, whereas the frequency information is normalized to the value of an external reference frequency.
Prior art gain normalization circuits typically employ a high precision multiplier in the PLL loop which is used to multiply the filtered and scaled phase error signal by the frequency gain KDCO of the oscillator. Due to the complexity of the high precision multiplier logic circuit, and the fact that it lies in a critical timing path, however, relatively large latencies are likely to be introduced into the loop in addition to high current consumption. In addition, changes made mid-packet or during the transmit operation to the frequency gain are likely to cause unwanted perturbations to the loop output.
It is desirable, therefore, to have a DCO gain normalization technique that does not require a high precision multiplier on the critical path in its implementation. In addition, it is desirable that the DCO gain normalization technique permit dynamic changes to the frequency gain without causing unwanted perturbations to the system.